In this post we look at the use of the latest power aware verification methodologies to “shift left” - to verify power architectures early and minimise bugs occurring in the power control network late in the design cycle.
Power management in modern socs
Modern SoCs are required to make efficient use of the power source to extend battery life or minimize energy requirements. Sophisticated power management strategies such as clock gating, multiple clock and power domains, or dynamic voltage and frequency scaling (DVFS) result in complex on-chip power networks. This adds significant complexity and effort to design verification, which must ensure the device operates correctly in numerous possible power states.
Capturing the power intent early in the design cycle
Complex SoCs may have a power architecture supporting a number of different power modes, resulting in numerous power states that must be checked to ensure that the device correctly enters and exits each state, and that transitions across power domains within the device are properly managed. The power architecture, describing power and clock domains and the desired power states, can be captured at an abstract level, in UPF format, known as the power intent. This can be simulated along with the RTL providing a reference model that can be used throughout the design cycle to ensure the corresponding power control network is correctly implemented. Being able to simulate the power intent early in the design cycle also enables different power architectures to be explored, in order to identify the preferred solution. The corresponding gate-level representation must also be verified to ensure the power network implementation, including power nets, clock gates, level shifters, state retention cells and isolation cells enable the device to operate correctly in the desired power states.
Tools & TECHNIQUES
This is the know-how and the tools you may need to tackle a complex modern Soc utilising the latest power integrity verification techniques.
- Metric driven verification, planning, tracking and reporting
- Power mode testcase development
- Power aware simulation and debug (RTL and gate level)
- Languages: Verilog, VHDL, SystemVerilog, e, UPF, CPF, Perl, Tcl, Python, C…
- EDA tools: Mentor-Questa, Veloce, Cadence-Incisive, Synopsys-VCS, MVSIM
conclusionPLAN EARLY - 'SHIFT LEFT' - AND AVOID PROBLEMS DOWN THE LINE
As with many of the verification techniques associated with SoC design, the message is - Don't make life difficult for yourself - projects are challenging enough without adding more risk and uncertainty. Gate-level verification and debug will ensure the power control network correctly implements the specified power intent.
Would you like more information on this topic? Our engineering department has prepared a technical datasheet on Power Integrity that you can download here:
If you want to discuss power integrity verfication techniques, and how they may benefit your own design projects, then contact us and we can put you in touch with an expert from the Design & Verification Team.
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