Mentor's U2U event in Munich was well attended this year - over 300 attendees from 20 different countries. The words on everyone's lips? - AI and Machine Learning. Especially innovation within the automotive sector, and applications using voice and image-based computing.
I attended to deliver a presentation for the Functional Verification & Emulation Track. As an engineer with many years experience , the metric driven methodology that we use in-house here at Sondrel is, in my opinion, a must-have tool to keep your SoC project on track. This was the subject of my presentation, and how we used Mentor's planning tool to support this. As part of the presentation I used a recent project case study to illustrate the methodology more specifically.
There were some great presentations this year. I couldn't get to all of them - but I will give a summary here of a couple of the keynotes that took an industry overview, as well as detailing my own presentation.
Keynote - Wally Rhines - Consolidation & Specialisation
Mentor CEO Wally Rhines was one of the keynotes at the event - and his presentation on the semiconductor industry was particularly interesting. I also had the pleasure of sitting next to him at the event dinner - he's a fascinating dinner companion, and we chatted about many things.
His keynote was entitled 'Semiconductor Consolidation versus Specialization'. He explained that traditional industries - for example mining and steel - have been driven to consolidate at maturity so that they continue to generate cash and increase profitability, despite very slow revenue growth. The semiconductor industry, Wally suggested, is fundamentally different. Semiconductors are consolidating in order to specialise. Amonst others, he gave the example of Broadcom, and its plan to acquire Qualcomm. This is because Broadcom wants to focus its efforts on data centres.
Keynote - Ravi Subramanian - Converging Technology Innovations
Ravi is the Vice President and General Manager of Mentor’s IC Verification Solutions Division. He talked about the remarkable breakthroughs in automotive, networking, and communication technology in recent years. The convergence of these technologies, he says, is driving innovation related to IoT and autonomous systems. He predicts that voice-based and vision-based computing will grow significantly in 2018 and beyond, and to support these technologies you need high computational SoCs. In order to successfully verify these emerging technologies, that are by their nature very complex, new approaches will have to be found to achieve comprehensive coverage within customer timescales.
My Presentation - Verification Methodology & Case Study
'Implementing Metric Driven Methodology that Accelerates Verification Predictability and Automation' was the - rather long! - title of my presentation.
At Sondrel - regardless of whether we are using a customer's own methodology - we also track the project using our own. That way, we feel confident that with our very strong review system there can be no surprises as the project pregresses, and we can achieve the most comprehensive coverage.
Our verification lifecycle is divided into 3 phases - a planning, a development and an execution phase. Each phase has its own sign-off criteria.
The planning phase defines the strategy for verifying a design under test, and two documents are developed during this phase
A Verification Plan Document
- Lists the cover points, checkers and testcases
- This plan links detailed feature lists to cover points, checkers and testcases, which allows you to track progress and measure it against the plan
- Milestones/Checkpoints are set for metrics
This document gives the detailed testbench architecture along with description of testbench components. It mainly should contain:
- Testbench Block Diagram
- Testbench Stimulus and Checking Mechanism
- VIP Details
- It also includes the description of the methodology and EDA tools used
We then have a verification planning sign-off, that comprises the following:
- The sign-off document lists a number of tasks that need to be completed to properly sign-off this phase and it is filled by stake holders
- The Project Manager, verification engineers and design engineer reviews the sign-off document along with the verification expert and a design expert
- The first review is called by the verification engineer verifying that block. This can be repeated a number of times to make sure all requirements of the sign-off document have been accomplished
With the planning phase complete, we can now transition into the second phase - Development. Here are the key tasks to complete in this phase:
- Testbench code must be readable, well commented and must strictly follow the Customer’s Methodology
- Testcases should be constrained random and should not use complex constraint that requires high compute resources
- Checkers/Scoreboards should be re-usable at the top level
The verification development sign-off document is filled in by the appointed team members. These can consist of the Project Manager, Verification Engineer, Design Engineer, Verification Expert, Design Expert. These people are also responsible for reviewing this phase.
Its now time to execute the plan. This involves execution of the test-cases developed in the development phase. The verification management tool in use generates functional and code coverage figures.
In the execution sign-off document, filled in by the Design Engineer and Verification Engineer, there is a review/multiple reviews to ensure that all coverage goals are met.
A recent project engagement involved our engineering team executing the design, dft, top level functional verification and block level verification using functional and formal methods for a client project. The design was ~400kgate.
The case study example showed how, with our own methodology and the planning tools from Mentor Questa, we successfully verified a complex hierarchical design on time for a client. It has already been proved in silicon. This case study concentrated on the functional verification elements of this particular engagement.
In the planning phase, Questa Testplan was used and MS Excel to create a TestPlan at Mentor's suggestion. We had to install a Questa add-in which is open source and freely available
In this particular project, the methodology used was UVM. Questa VIPs were integrated as monitors for Protocol Check and to collect Functional Coverage. Assertions were used for specific interfaces e.g.: QChannels, PChannels. Metrics like Code, Branch, Toggle, FEC, Functional and Assertions Coverages were collected and measured.
In conclusion, by following all the best practices, and using a Verification Planner, we were able to achieve predictability and helped us keep a tab on our verification effort .
The complex nature of modern SoC designs means that you need a strong review system to keep on track of your verification efforts. Technology innovations in AI related applications will all mean one thing - processing and analysing large amounts of data, and our challenge is how to continue to give comprehensive verification coverage to these increasingly complex designs.
Sondrel provide consultancy services to companies looking to build silicon chip solutions for their products and applications. We have a deep understanding of graphics, image processing and multimedia SoC design, through many years of project work.