Almost every aspect of electronic design has at least some focus on low power, particularly with mobile devices dominating the consumer market. Designers are faced with OEMs demanding that the size of the device is reduced and contending with battery technology that is lagging far behind. The challenge for chip designers is therefore to squeeze the best possible power performance out of a chip, while working on the bleeding edge of process technology, delivering improved performance and all on a budget. No easy task.
Low power ic design is a challenge in designing both applications for mobile use and tethered applications - the problems are the same, just on a bigger scale and the same attention to detail is required. In dealing with these higher power applications, leakage along with transient current are two of the biggest problems. With multiple voltage domains switching large amounts of current on and off, the chip needs enough decoupling to supply power but without causing leakage. Sondrel has done a lot of physical implementation with different EDA Tools across a number of large designs and through this has been able to carry out analysis on all the power aspects and accurately establish the optimum decoupling to apply. When dealing with peaks of over 150Amps getting this right is essential.
Transient current spikes when switching parts of a circuit on and off
Simply splitting any chip design into several power domains allows some parts to be completely shut off depending on the requirement. This simple technique can result in impressive power savings when done well. Sondrel is often asked if there are other areas of lower power design that can be addressed: Mixed Vt flow is a good place to start, it is well supported by the EDA companies much like multiple power domains and also is one of the oldest techniques. It is based on the principle that certain areas of a design (the cells) operate at a higher threshold voltage, which makes them slower but less leaky, whereas other cells operate at lower threshold voltages, which operate faster but are more leaky and energy wasteful. Getting reasonable results is easy with the automated tools from all the EDA vendors, but even better results can be obtained by refined techniques closely linked to the sign-off flow.
A bigger challenge at the other extreme are the clock tree optimisation techniques, where aggressively adding clock gates into the physical design selectively reduces speed and therefore power in specific areas of the chip. Synopsys has an established approach, which is a perfect example of where clock gating is done during synthesis with no knowledge of layout required. A relative novice can obtain good power savings in a reasonable cycle time using simple clock tree optimisation.
One other key area is the management of the implementation flow for the FD-SOI and in particular the back-biasing strategy. Through this technique, it’s possible to modulate the bulk voltage of the transistors, change the threshold voltage and have a better tradeoff between leakage and the other PPA targets. The Back-biasing flow requires a specialised understanding of multivoltage PnR methodology, that includes implementation, checking and signoff.
Design for low power isn’t easy but by addressing key areas in the physical implementation stage you can keep power and leakage down without having to completely redesign the chip.
Sondrel provide engineering support and consultancy services to our customers across the globe, from spec to silicon. We are an ARM Approved Design Partner.
You can download a datasheet that summarises advanced low power design techniques here:
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