Implementation Techniques of IP Cores for Optimum PPA Results

Physical Implementation Jun 24, 2016 9:48:59 AM

Jun 24, 2016 9:48:59 AM


In an ever competitive market place design teams are often faced with the challenge of providing differentiated products by achieving market leading power performance and area (PPA) targets to drive future sales and market share. To do this you need a deep understanding of implementing IP cores like ARM, ATOM and MIPS to meet these targets without incurring additional project costs or impacting time to market. Tough going...

... but not impossible. You do need the processes, methodology and know-how to understand the challenges and choose the implementation techniques that will deliver on those targets.



For leading edge implementation, the more tools you have at your disposal, the more creative you can be. With an RTL2GDSII design flow that is optimised for multiple EDA flows, library vendors and technology nodes you can create solutions that can achieve your PPA targets, through:

  1. Power Reduction

    1. Choice of library

    2. Power aware implementation ( power gating, activity based synthesis, back biasing, CCD optimisation, MV macro )

  2. Timing Closure

    1. SBOCV, POCV

    2. Physical aware timing eco

    3. IR drop aware STA

  3. Area Reduction

    1. Timing optimisation for high utilisation design

    2. Area Recovery


IP hardening in a wider sense doesn't only mean timing+drc+power closure of a block, but also the creation of an eco-system around the delivered block, which means configurable flows, library composition and various floorplan styles and shapes.

In this way, you can develop advanced techniques for low power, a high number of process corners, dynamic voltage and frequency scaling, and single dual and quad cores for example.


To hit those challenging PPA targets, a holistic eco-system approach, coupled with a solid and repeatable methodology will help you to find those precious leading edge design improvements that customers crave.

Sondrel is an ARM Approved Design Partner, and provides IP Hardening services for customers across the globe. With 5 international design centers, an accredited ISO27001 certification and its award winning Helium 8 design flow and methodology, it has proven project expertise and delivery over hundreds of designs down to 14nm.

You can download a datasheet on IP Hardening here

IP Hardening Datasheet

Or you can contact us to discuss your particular project requirements

Contact Us



Physical Implementation

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