Whatever the end application might be for your IC, power, and how you design and manage power will be fundamental. Large network and server SoC designs and even cabin based automotive chips must run to strict heat dissipation targets, whilst mobile devices and Internet of Things (IoT) type devices require very long battery life. All are enabled by specialist power management ic design techniques. In this blog we will highlight the key areas in a design where you can optimise and manage power.
It‘s clear that power optimisation is a key consideration from system design through RTL, to physical implementation, with evolving challenges at every level. As an ic design services consultancy, we deal with multiple projects every year across different applications. Some design challenges are similar across different applications, for example our expertise in designing for mobile can inform and help us with certain IoT designs. Or our expertise in dealing with designs for large network servers can transfer over to certain automotive chip designs.
KEY Areas where you can optimise & MANAGE Power:
- Minimising Dynamic Power through clock tree optimisation techniques
- Targeting any part of the chip that can be switched off by gating the clocks in that area where granularity is small
- System Level Power Control
- Dynamic voltage scaling or Adaptive voltage frequency scaling
- Advanced Clock Tree Synthesis
- Clocks represent the largest source of dynamic power usage, making clock tree synthesis (CTS) and optimisation a good place to achieve significant power savings
- MCMM clock tree synthesis
- Clock Gating Minimises Clock Switching
- This is a common technique for reducing power by shutting off the clock to unused registers
- Along with power-aware clock gate placement, CTS should also automatically perform clock gate cloning and de-cloning to optimise and balance the load on the clock tree network
- DFT Design
- DfT has to be power aware
- In test modes the switching activity can be far higher than in operation and consequently use a lot of power, resulting in heat or more critically signal integrity problems during test
- ambient temperature can potentially be better controlled in the test environment, the air-flow and use of heat-sinks cannot
- UPF Aware
- The Unified Power Format (UPF) describes the power architecture from the power design point of view
- System engineering defines which parts of the chip can be managed with respect to power and this leads to the UPF definition that design tools then use
- RTL to GDS
- It’s hard at the RTL level to do a “low power” check properly when performing the Synthesis from RTL to netlist, no matter what tools are used simply because of the complexity of working with multiple power domains and voltage levels. Due to tool immaturity designers are forced to rely on engineering teams’ experience to do ECOs ‘by hand’ to generate a proper netlist.
Power Management isn’t straightforward. PPA targets are often aggressive, time to market another challenge. One of main issues is that all EDA tools, no matter how new, are constantly evolving and chasing the requirements of the more advanced geometries and that these frequently have negative implications on design-for-test functions. Being tool neutral, Sondrel has flexibility to look at all the options, and pick the right tool for the task at hand. That’s a good start. It’s then a question of your engineering team using its experience and expertise to apply more refined techniques to a design to achieve the PPA targets necessary for the success of the project and the end product.
You can read more on the subject of designing for power by downloading a free datasheet on Advanced Low Power Design prepared by the Sondrel engineering team.
If you would like to discuss your PPA targets for a particular project with the Sondrel team, and how we may be able to assist you, please click on the link below, fill out a very simple form with your contact details, and we will call you staight back.