Functional Verification can enable your verification environment to “shift left”, starting verification early in the design cycle by streamlining testbench development, facilitating faster turnaround times and high quality reliable designs.
TECHNIQUES & TOOLS
Designing a modern SoC is complex, challenging and costly. In order to manage the risk of such projects, maintain the quality of the product and hit your time to market dealine, a 'shift left' strategy is the way forward.
Functional verification is often the most resource intensive and costly part of the SoC hardware design process. However, it is critical to the efficiency and effectiveness of your project. So what is involved? Here is a list of the techniques that can be used, and the tools to do the job:
Metric driven verification, planning, tracking & reporting
VIP development, porting & configuration
Testcase development - system or unit level
Simulation and debug
Standards: eRM, VMM, UVM, IP-XACT, UCIS, AMBA, MIPI, DDR, USB…
Languages: Verilog, VHDL, SystemVerilog, e, SVA, PSL, Tcl, Perl, Python, C/C++
EDA tools: Mentor-Questa, Cadence-Incisive & vManager, Synopsys-VCS, Verdi and Certitude
Utilising a wide range of verification skills you can apply simulation based techniques at IP block level, sub-system or full chip level. And using the latest technologies, such as SystemVerilog, assertion based verification (ABV), UVM and metric driven verification can increase productivity during verification projects.
- SystemVerilog has built-in capabilities designed to support advanced functional verification such as constrained random stimuli, assertions, and coverage points.
- UVM provides standard libraries designed to make it easier to leverage the capabilities of SystemVerilog and create re-usable verification IP (VIP) components supporting rapid testbench development. The latest simulation tools are optimized for executing UVM testbenches enabling faster testcase throughput.
- Adoption of ABV allows design intent to be captured at source so that when errors are detected by assertions, the source of the error is easily traced. Assertions greatly aid observability and reduce time to debug designs.
Through your Test plans, Testbenches and Test Stimuli, you will be analysing, reporting and collaborating with the designers to resolve any bugs that are encountered throughout the design process. The emphasis on verification techniques early on in the design cycle will help you to achieve faster turnaround times and high quality reliable designs.
If you would like read further information on this topic you can download a datasheet on Functional Verification prepared by the Sondrel Engineering Team. You can also opt in to subscribe to the Sondrel blog, where we will be covering more verification stategies, and other ic design techniques.