INTRODUCTIONFPGAs offer an alternative to an ASIC, where their re-programmability, often lower engineering costs and fast time to market, can offer benefits. In this blog we will explore these benefits and the current techniques that can maximise the efficiency of your FPGA.
An understanding of advanced design and verification methods like RTL synthesis, STA and metric driven verification, as well as FPGA place and route, can significantly improve the time to market for your design.
increased complexity is supported by modern FPGA architectures
In house FPGA verification is often based around simple HDL design and testbenches. The increased complexity supported by modern FPGA architectures, however, means these methods can lead to critical bugs that are very hard to find. This in turn can lead to many design iterations, and an increased risk of field failures, the cost of which can be significant and is often under-estimated.
What can best in class design achieve?
- Benefit from the latest metric driven verification methodologies e.g. UVM, ABV, constrained random, formal verification
- Achieve faster time-to-debug and design bring up
- Achieve higher quality designs with less effort or cost.
- Realise fewer field failures
Today’s complex FPGAs can support designs similar in complexity to many SoCs and ASICs. The design and verification of these is both resource intensive and time consuming, requiring specialist skills including many more familiar to ASIC experts.
Sondrel uses the latest design knowhow and verification methodologies to help our clients address higher FPGA complexity whilst improving productivity, producing higher quality designs, faster.
Traditional approaches to FPGA verification rely on using simple HDL testbenches and directed tests. The weakness of directed tests for more complex designs is they only cover conditions that have been anticipated by the verifier. Many bugs can slip through and only get identified when the FPGA is running in the lab, where these bugs are difficult to debug and they need to be reproduced in the simulation environment. This iterative approach is very time consuming and high risk. Applying metric driven, constrained random methodologies allows the design to be exercised much more exhaustively with a small set of easily maintainable and reusable tests, ensuring a much more robust design, before the design is validated in the lab, minimising the time to debug.
Process and Methodology
This is the process and methodology that Sondrel engineers follow for a design & verification engagement.
Specification Planning Phase
Detailed specifications and verification plans are developed and agreed with the customer, along with acceptance tests.
Design specifications are realised in verilog. Where applicable support for power modes can be developed and a complete set of tool constraints used to guide the synthesis, place and route tools are created, ensuring optimal performance, utilisation and power are achieved
The verilog code is synthesised to a netlist which is mapped onto IP, logic and routing resources using the FPGA vendors place and route tools.
Verification and Validation
Advanced functional verification techniques are used to verify the verilog code to high functional and code coverage goals making use of advanced verification technologies like SystemVerilog, UVM and reusable verification IP components. Bugs can be avoided by instrumenting RTL code with assertions that can be used to verify code statically before simulation, minimising the number of simulation jobs required to debug the design and reducing time to debug.
Validation of the design is performed in the lab using board level test methods.
Sondrel’s engineers have a wide range of design and verification skills that can address FPGA based designs of all complexities targeted at a variety of market segments including aerospace and automotive.
Sondrel can support your existing approach or enhance your capabilities by providing rapid access to the latest technologies such as ARM processors, on-chip interconnects and high speed interfaces (e.g. DDR, USB, PCIe). Our expertise in advanced methodologies such as synthesis, STA, FPGA place and route, metric driven verification and formal methods increases productivity during FPGA projects and can significantly increase design quality.
Download our datasheet on FPGA Design & Verification for additional details: