This blog looks at a case study of a recent engagement with a leading wireless communications supplier, and involved the design of a machine to machine IoT ASIC which will be used over a Zigbee Network. We worked on the DfT and Physical Implementation of the design.
The purpose of the engagement was to reduce the area size and power consumption of an existing version of the design. ZigBee is typically used for consumer and industrial equipment that requires short-range low-rate wireless data transfer, particularly those that require long battery life and secure networking.
short-range low-rate wireless data transfer over a Zigbee Network
The principle challenges of this multi project wafer tape-out design was its very aggressive timeline, and the area target set to reduce the cost of manufacture and reduce the power consumption of the chip.
A four man team, ramping to eight, worked on this six month engagement. The Sondrel team was based in Design Centre sites in Europe, Morocco and China. This was a fixed price engagement, using Sondrel tools and the Sondrel Helium 8 Implementation flow.
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- 55nm GF LP x NVM
- Area of 10mm2
- Frequency: 192Mhz
DFT (Design for Testability)
- Transition Fault
- Scan Compression
- Power Gating
- Physical Aware Synthesis
- Multi-corner Implementation
With a late RTL release, this project ran on a very tight schedule. From a design flow perspective, the engineering team effort concentrated on the following:
- Area: It had an aggressive requirement for a reduction in area, the benefit being two-fold: saving on the cost of manufacture, and that the device consumes less power.
- Schedule: This was a multi project wafer tape-out, so there was no flexibility within the schedule to move the tape-out date. This proved to be challenging due to the late delivery of the RTL to the design team.
- Timing signoff: multi-mode/multi-corner timing verification was required.
- Electro migration (EM) signoff: The power sign off was important, because of the chip application, and therefore required power gating implementation to keep the power consumption to a minimum.
The Process & Methodology
Sondrel uses a proprietary design flow and methodology called Helium that incorporates the specific design targets and techniques needed to ensure that project requirements are met. A version of Helium specific to low power design – Helium 8P was used for this project:
- partitioned into a number of discrete Phases
- well-defined entry and exit criteria to ensure that at each stage data is correct and fit for purpose
- well defined conventions, each designer knows Helium terminology
- detailed and classified procedure documents
This is an example of the challenges thrown at designers in real time. The PPA requirements involved a 20% area reduction, on the same technology node, compared to the previous version of this design. The RTL release was late - this is the real world! - so no wriggle room in the project schedule. As a team, you have to manage the tasks at hand as efficiently as possible.
Sondrel works on much larger and more complex designs - but even with smaller designs, that will be more prolific in the IoT sector, you are still asked to take the design to the max.
And there's never enough time, right? Such is the lot of chip designers...
If you would like to know more about the designs and engagements that Sondrel support, why not get in touch? We can provide you with additional information on the technologies or applications that you are working on.
You can also download a version of the case study described