Why is there a Need for This?
Quite simply, if you don't get this right you could be looking at a partial, or complete failure of the chip to function. And this will cost time and money to go and find the problem and to correct it. It is an increasingly critical part of the design process as the node size reduces, and you need to employ engineering resources with a deep understanding of I/O behavioural and electrical requirements, using advanced EDA software tools, to tackle this.
Package Simulation at Advanced Nodes
A modern high-performance SoC device requires progressively wider and more complex I/O interfaces to meet increasing data throughput requirements. These interfaces are designed using advanced process nodes that are expected to perform within tight timing margins, whilst operating at close to 1V supply voltages.
The structure of the electrical path from the silicon chip, across the package substrate and down to the PCB transmission lines up to the external load, is influenced by several direct or indirect effects. For example, issues like simultaneous switching and noise, crosstalk coupling and impedance matching.
In a complex structure, the handcrafted Spice simulation is still the golden reference, however, it could not practically handle complexity where an advanced I/O schema includes thousands of signals, running in the GHz regime. Also, the model of the I/O cells, the RDL and the substrate structure require state-of-the art 3D extractors.
What services form part of an I/O Simulation?
Several services are considered for a comprehensive I/O simulation:
- Handling the interaction with the package house and the foundry
- Definition and sizing of the pad IO rings
- Design and optimisation of the RDL routing (high dense and smallest pitch)
- Chip Power Model generation
- I/O model generation and integration of specific views like IBIS and Spice.
- Bumps assignment/alignment, substrate and package IBIS simulation to verify cross talk and signal integrates
- Budgeting of the power/signal integrity/channel insertion loss (ISI) at physical design, package, and board level.
- Package simulation with IBIS model and package RLC
- Eye diagram with S-parameter
- Time and frequency domain simulations
- Resonance and impedance matching
Package Substrate Simulation is an increasingly time consuming and complex task at leading edge nodes. Ensure you have the engineering expertise and latest software tools to do the job properly - otherwise, you could be looking at the partial or full failure of your chip.
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The Sondrel engineering team work with customers across various market sectors to provide tailored design service solutions focussed on Power Performance and Area target specifications. If you would like to discuss your project requirements, why not request a call?